Post Silicon Validation Engineer

Silicon validation experience, preferably in the area of SERDES, DDR or high-speed interface design. BE or ME Graduate
Experience in system marginality validation
Good understanding of lab equipment and measurement techniques for high-speed interfaces. High speed scopes, probes, spectrum analyzers, BERTs.
Knowledge of board and package design, signal integrity and power integrity a plus
Knowledge of DDR trainings and memory system operation a plus
Software proficiency for python test scripting, data handling and reporting
Laboratory experience, including hands-on use of equipment: oscilloscope, logic analyzer, etc.
Excellent problem-solving skills, good communication skills and ability to work cooperatively in a team environment
Debug issues with SOC IP and boards as needed.

Bring-up & Silicon Characterization
Validation of C2C, PCIe, CXL, DDRx, LPDDR controller/chips
Validation of SRAM and Vmin optimization
Scripting and test data processing to extract meaningful signals
Develop and integrate software test applications for effective product stress and SLT screening and collaborate with software teams to evaluate system performance and HW/SW interaction under various conditions.
SLT test time optimization, including shift right strategies STL to ATE
Test time, DPM, & yield optimization for effective production screens
Root cause analysis and RMA processing
Mentor Junior Engineers when the project need arises
Experience in Post Silicon Electrical Validation of server processors (if server processor is too specific, you can remove server)