Implementation Timing / STA Design Engineer – ASICS Engineering
| Company | Qualcomm |
|---|---|
| Location | San Diego, CA, USA |
| Salary | $134500 – $215000 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Mid Level |
Requirements
- Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Proficient with tools such as Primetime, Fishtail/TCM.
- Scripting skills in Tcl, Perl, or Python.
Responsibilities
- Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis.
- Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks.
- Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores.
- Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing.
- Analyze timing across modes and corners, understand concepts like path pessimism and margins.
Preferred Qualifications
- Scripting skills in Tcl, Perl, or Python.