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Signal Integrity Engineer
| Company | Intel |
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| Location | Hillsboro, OR, USA |
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| Salary | $139710 – $197230 |
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| Type | Full-Time |
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| Degrees | Bachelor’s, Master’s |
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| Experience Level | Mid Level |
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Requirements
- Bachelor’s with 4+ years of experience or Master’s with 3+ years in Electrical Engineering, Computer Engineering or related field
- 3+ years of combined experience in Electrical/electromagnetic and signal integrity fundamentals
- 3+ years of combined experience in High speed and low speed I/O (Input/Output), for example in PCIe, USB, Display, etc that consume data and power for interconnectivity and compatibility across a multitude of products
- 3+ years of combined experience in Experience with the use, understanding, and optimization of I/O to monitor input signals
- 3+ years of combined experience in 3D/2D EM simulation tools like HFSS, Q3D, ADS, HSPICE, etc.
Responsibilities
- Delivering signal integrity solutions for large, complex highspeed platforms, boards, and packages
- Developing a viable space for all interconnects including 2D and 3D models extracts of electrical structures for the entire dietodie interconnect
- Defining signal integrity rules, reviews implementation, documents characterization and measurement reports, and improves and optimizes design margins
- Applying knowledge of signal integrity design and tradeoffs to perform simulations of interconnect and guide package and platform physical implementation, and designs and characterizes test structures to correlate simulations and measurements for interconnects using intricate highspeed equipment and debugs challenges
- Developing electrical specifications and new industry standard interconnect specifications to guide consortiums for nextgeneration interfaces
- Documenting and providing implementation guidelines to the end customers as part of the platform design guide
- Collaborating with IP design teams and silicon integration teams to ensure the IP and SoC designs maximize the platform level solution space to meet targeted product landing zone requirements and minimize quality degradation (e.g., attenuation, crosstalk, jitter, power noise) and cost.
Preferred Qualifications
- Ability to use fundamental electrical engineering principles such as power, passive and active circuit component operations, and signals to validate and test for functionality, debug signal, and power integrity issues of high-speed serial interfaces on platforms
- Knowledge of basic electronic equipment including digital oscilloscope, DMM, network analyzer etc, a plus
- Knowledge of boards and ecosystem ingredients
- Basic understanding of adjacent domains like RFI-EMC, Memory signal integrity, power integrity etc.
- Good communication skills and an excellent team player.
