Staff Digital Verification Engineer
| Company | Northrop Grumman |
|---|---|
| Location | Halethorpe, MD, USA |
| Salary | $173200 – $259800 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Expert or higher |
Requirements
- Bachelor’s degree in a technical area (BSEE or other Engineering discipline preferred) with 12 years of relevant experience (10 years with technical MS; 7 years with PhD)
- Experience in HDL (VHDL/Verilog) and HVL (SystemVerilog)
- Experience with SystemVerilog Assertions (SVA)
- Knowledge of Universal Verification Methodology (UVM)
- Familiarity with a coverage driven verification methodology from planning through closure
- Knowledge of industry standard interfaces
- Experience with object-oriented programming languages and concepts
- US Citizen and able to obtain and maintain a TS/SCI clearance with Polygraph.
Responsibilities
-
No responsibilities provided.
Preferred Qualifications
- Advanced Degree either MS or PhD
- Experience with Mentor Graphics and/or Cadence Verification tools – FPGA/ASIC Design experience
- Experience with scripting languages (Bash, Perl, Python, Tcl)
- Current TS/SCI security clearance with Polygraph