Signal Integrity Engineer
| Company | Intel |
|---|---|
| Location | Santa Clara, CA, USA, Folsom, CA, USA |
| Salary | $139710 – $197230 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s |
| Experience Level | Mid Level, Senior |
Requirements
- Bachelor’s Degree in Electrical Engineering or Computer Engineering with 3+ years of experience in Signal Integrity
- OR a Masters Degree in Electrical Engineering or Computer Engineering with 2+ years of experience in Signal Integrity
Responsibilities
- Delivers signal integrity solutions for large, complex high speed platforms, boards, and packages.
- Develops a viable space for all interconnects including 2D and 3D models extracts of electrical structures for the entire die to die interconnect.
- Defines signal integrity rules, reviews implementation, documents characterization and measurement reports, and improves and optimizes design margins.
- Applies knowledge of signal integrity design and tradeoffs to perform simulations of interconnect and guide package and platform physical implementation, and designs and characterizes test structures to correlate simulations and measurements for interconnects using intricate highspeed equipment and debugs challenges.
- Develops electrical specifications and new industry standard interconnect specifications to guide consortiums for next generation interfaces.
- Documents and provides implementation guidelines to the end customers as part of the platform design guide.
- Collaborates with IP design teams and silicon integration teams to ensure the IP and SoC designs maximize the platform level solution space to meet targeted product landing zone requirements and minimize quality degradation (e.g., attenuation, crosstalk, jitter, power noise) and cost.
Preferred Qualifications
- Knowledge of Silicon, Package and PCB layouts and SI design practices
- Good understanding of transmission line and network theory, microwave engineering
- Expertise in circuit simulation with Spice, ADS and EMextractions with commercially available solvers from Ansys HFSS, Q3D, Cadence PowerSI, Synopsys HSpice and Keysight ADS
- Familiarity with DDR and SERDES interfaces, such as LPDDR5/5x/6, GDDR6/7, PCIe Gen5/6, HDMI, eDP, I3C, SVID, etc.
- Basic understanding of EMI/RFI theory and analysis
- Experienced in full channel analysis in frequency and time domain for DDR and SERDES interfaces