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CPU RTL Engineer
| Company | Google |
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| Location | Austin, TX, USA |
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| Salary | $132000 – $189000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Mid Level |
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Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques.
Responsibilities
- Contribute to CPU front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
- Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements, facilitate final decision making.
- Deliver designs meeting Power, performance and area (PPA) goals with production quality.
- Become familiar with state-of-the-art techniques for one or more processor functional blocks. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.
Preferred Qualifications
- Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Benefits
