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Analog Design Architect
| Company | Cadence Design Systems |
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| Location | San Jose, CA, USA |
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| Salary | $169400 – $314600 |
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| Type | Full-Time |
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| Degrees | Master’s, PhD |
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| Experience Level | Senior, Expert or higher |
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Requirements
- Minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development
- Thorough understanding of jitter and signal equalization techniques
- Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
- Proficiency in using CAD tools for circuit simulation, layout, and physical verification
- Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
- MS or PhD in EE
Responsibilities
- Design and develop analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.
Preferred Qualifications
- Working knowledge of a set of common SerDes standards and their electrical requirements is a plus
- Cadence tool experience is a plus
- Lab test experience is a plus
- Design experience at >10Gbps and in <28nm technologies is a plus
