Analog Mixed-Signal Design Engineer

Analog Mixed-Signal Design Engineer

Requirements

• MS or PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in advanced node high speed analog and mixed signal development for SerDes and data center networking with primary focus on clock generation and distribution.
• Experience in designing low jitter, low power PLL, VCO and clocking circuitry in advanced CMOS nodes.
• Experience with analog and ADC based Clock and Data Recovery (CDR) is highly desirable.
• Deep understanding of advanced clock distribution techniques such as resonant and traveling wave clocking.
• Proficiency in electromagnetic tools like EMX or similar.
• Design and tape out experience in advanced nodes such as 5nm and 3nm FinFET is a must.
• Deep understanding of signal integrity and power integrity for high-speed designs.
• Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development.
• Strong analytical thinking and problem-solving skills with excellent attention to details.
• Must be organized, self-motivated and able to work effectively across internal and end customers teams.
• Must have excellent knowledge/experience with TSMC 7nm-5nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.

Responsibilities

• Develop analog and clocking blocks for high-speed wireline and SerDes connectivity applications.

Preferred Qualifications

• Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.
• Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.
• Excellent time and task management, and interpersonal skills.
• Willingness to travel when required.