ASIC Design Engineer – Low Power AI Subsystems – ASICS Engineering

ASIC Design Engineer – Low Power AI Subsystems – ASICS Engineering

Requirements

• Professional or academic ASIC hardware design and/or implementation experience. New graduates should have ASIC design internship or co-op experience.
• Proficiency with Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
• Good understanding of ASIC/VLSI concepts
• Experience in logic synthesis using Synopsis and/or Cadence tools.

Responsibilities

• Design high speed, low power digital hardware solutions
• Contribute to definition, micro-architecture and documentation
• Collaborate closely with the Verification team to test, debug and close coverage on the design
• Evaluate synthesis results to verify the design meets the speed, power and area targets
• Support internal hardware integration, SW teams around the world
• Resolve architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision
• Use of various design tools (VCS, DC, Linting, CDC, LEC, CLP etc.) to check and improve design quality
• Provide ideas and further the innovation of ASICs, IP cores, and process flows

Preferred Qualifications

• 2+ years of ASIC hardware design related experience
• Working knowledge of UPF specification
• Experience with power analysis, power modeling and low power RTL design.
• Experience with clock domain crossing techniques
• Experience with a subset of DC, FC, PTPX, Power Compiler, Primetime, Modeltech, VCS, power theatre, etc.)
• Experience with design rule check (Spyglass, etc.), Formal verification (Formality, LEC, etc.) and/or Power analysis and simulation
• Scripting skills (Python , PERL, TCL or C)
• Knowledge of bus interface protocols (APB, AHB, AXI)
• Experience with post-silicon debug
• Experience with UVM
• Experience with automotive safety concepts and standards such as ISO26262