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ASIC Design Verification Engineer – Machine Learning
| Company | Google |
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| Location | Madison, WI, USA |
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| Salary | $132000 – $189000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Mid Level, Senior |
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Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
- 3 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage).
Responsibilities
- Plan the verification of digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Preferred Qualifications
- Master’s degree or PhD in Electrical Engineering.
- 6 years of experience in design verification.
- Experience with industry-standard simulators, revision control systems and regression systems.
- Experienced with the full verification life cycle.
