ASIC Engineer – IP Design – Silicon

ASIC Engineer – IP Design – Silicon

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• Experience with a scripting language like Python or Perl.
• Experience with ARM-based SoCs, interconnects and ASIC methodology.

Responsibilities

• Define microarchitecture details, block diagrams, data flow, pipelines, etc.
• Perform RTL development (SystemVerilog), debug functional/performance simulations.
• Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
• Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
• Communicate and work with multi-disciplined and multi-site teams.

Preferred Qualifications

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 8 years of industry experience with IP design.
• Experience with methodologies for low power estimation, timing closure, synthesis.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).