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ASIC Physical Design Engineer
| Company | Google |
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| Location | Sunnyvale, CA, USA |
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| Salary | $132000 – $189000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Senior |
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Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in ASIC physical design and methodologies in advanced process nodes.
- Experience with place and route EDA CAD tools, commands, debug, and custom techniques via Tcl or GUI interaction.
- Experience with EMIR parameters, analysis, violation mitigation and tradeoffs related to power grid design and augmentation.
- Experience in advanced process nodes with base and metal layer DRC analyses and problem resolution.
Responsibilities
- Work on physical design including place and route, EMIR, static timing, and physical verification.
- Go beyond automated flow execution and use industry standard EDA CAD tools to perform custom design work, to provide customized solutions to specific problems, and to enhance PPA.
Preferred Qualifications
- Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with IO pads, RDL route, bump mapping, and boundary scan.
- Experience with physical IP integration (e.g. memories, IO’s, analog PHYs).
- Experience with silicon interposer design.
- Experience crafting physical design automation flows.
Benefits
No information provided on Benefits.
