ASIC Principal Engineer
| Company | SEAKR Engineering |
|---|---|
| Location | Cherry Hills Village, CO, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | Bachelor’s |
| Experience Level | Expert or higher |
Requirements
- ASIC design tools and techniques
- Synthesis, Static Timing Analysis, Design for Test, and Formal Verification
- Strong RTL background and ability to drive verification
- Working with designers and system engineers to analyze ASIC requirements
- ASIC implementation experience for hierarchical designs
- Defining and maintaining ASIC design and methodology guidelines
- Defining and maintaining ASIC signoff documentation and checklists
- A Bachelor’s degree in Electrical Engineering is required
- Must have at least 10 years of ASIC implementation experience
Responsibilities
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No responsibilities provided.
Preferred Qualifications
- Working knowledge of multiple EDA suppliers; Synopsys, Cadence, or Mentor
- Previously debugged test vectors on the test floor
- Experience with multiple interface IP; DDR, UCIe, High Speed SERDES, ADC/DACs
- Ability to write constraints to properly sign-off the design for test
- DFT experience in 32nm and below technology nodes
- TKL and Python scripting, and Git and Subversion revision control tools
- Experience with Synopsys or Cadence Static Timing Analysis
- Hierarchical synthesis techniques and clock gating for power reduction
- Primetime SI, DFT Advisor and Fastscan/Tetramax
- Tessent RAM self-test / self-repair tools
- Logical Equivalency checking and power analysis
- Synopsys or Cadence Physical Design