Camera DV Engineer – Camera Engineering
| Company | Qualcomm |
|---|---|
| Location | San Diego, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Mid Level |
Requirements
- Experience with design verification defining test plans, developing verification infrastructure using OOP and execution of defined test plans to meet required Metrics of Closure
- Expertise with Hardware verification languages (HVL) such as System Verilog testbench (OVM/UVM)
- Development of Directed and Constrained Random stimulus
- Strong Digital Design concepts and debugging skills with expertise in traversing Verilog/System-Verilog RTL
Responsibilities
- Engage in Technical discussions across Design/Software/Firmware teams to review / influence optimal imaging solutions and data flows
- Implement test benches to adapt to new requirements by extensively applying object-oriented concepts & UVM methodology
- Write parameterized & scalable verification plans
- Write complex constraints and sequences to create corner case Algorithm and pipeline tuning scenarios
- Verify functionality and Use-Case Power / Performance KPI’s are met.
- Use Simulation/Formal/Assertion/Emulation flows to close on Functional and Code coverages
- Debug complex issues across multiple verification platforms
- Writes clear and detailed technical documentation and feature descriptions to guide users and/or customers to use or implement output.
Preferred Qualifications
-
No preferred qualifications provided.