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CPU Physical Design Pathfinding Engineer – CPU Engineering
| Company | Qualcomm |
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| Location | San Diego, CA, USA |
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| Salary | $211900 – $317900 |
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| Type | Full-Time |
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| Degrees | |
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| Experience Level | Senior, Expert or higher |
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Requirements
- Experience with Synthesis, place and route and signoff timing/power analysis.
- Knowledge of high performance and low power implementation techniques
- Proficiency in scripting (TCL, Python, Perl)
Responsibilities
- Collaborate with cross-functional teams (RTL, Physical Design, Circuits, CAD) to address critical physical design challenges in CPU implementations.
- Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets.
- Coordinate with CPU Software, Architecture, and RTL teams to understand various CPU use cases and propose impactful PPA optimizations.
- Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to CPU designs.
- Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs.
- Partner with Process, SoC and Post-silicon teams to analyze, improve design implementations
Preferred Qualifications
- MS degree in Electrical Engineering with 14+ years of practical experience.
- Preference for experience in deep submicron process technology nodes.
- Experience in CPU PPA optimization is advantageous.
- Knowledge of library cells and optimizations.
- Solid understanding of industry-standard tools for synthesis, place & route, and tapeout flows.
- Strong data analytical skills to identify and address physical design issues.
- Experience in pre-post silicon correlation
