CPU Sta CAD Engineer – CPU Engineering
| Company | Qualcomm |
|---|---|
| Location | San Diego, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Senior, Expert or higher |
Requirements
- Industry experience of Static Timing Analysis (STA) on cutting edge technology nodes
- Programming/Scripting skills (Python and Tcl in particular) and an automation mindset.
- Coding with a focus on quality and reusability. Leverage static checking, Test Driven Development, CI/CD, etc to achieve high quality software
- Experienced in generating/optimizing/automating timing ECO closure
- Detailed understanding of STA concepts (e.g.: LVF/CCS/SSI/NBTI) and how they impact margins/derates
- Debugging/Support with project deadlines in mind
- Synthesis/PnR experience with a focus on PPA optimization.
- Collaborate with EDA partners to determine/drive optimal and cutting-edge solutions
Responsibilities
- Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area
- Maintain, support and debug STA and timing closure (ECO) flows, and resolve project-specific issues
- Work closely with worldwide CPU physical design teams, and provide methodology guidance and tools/flows support.
- Work with EDA vendors to define roadmap and to resolve tool issues.
Preferred Qualifications
- Web/Database/Dashboards/Visualization experience a plus.