Design Verification – Senior Staff Engineer

Design Verification – Senior Staff Engineer

Requirements

• Bachelor or Master’s degree in Electrical Engineering or related fields with 5+ years of experience.
• Proficient in System Verilog and object-oriented programming
• Well versed with UVM/VMM methodology
• Has worked on complex chips such as CPUs, GPUs, Switches, Machine Learning chips etc.
• Has led or participated in full chip, subsystem, and block level verification
• Test bench development including agents, drivers, checkers, interfaces etc. for a complex design
• Knowledge and experience in memory interface subsystem (DDR, LPDDR, HBM), NOCs, D2D, embedded processors (ARM, RISCV, etc.) and in complex multi-chip verification environment
• Has experienced full verification cycle from architecture to tapeout with good understanding of testplan development, debug, coverage closure and gate level simulation
• Experience with analysis and closure of code and functional coverage

Responsibilities

• Working on the verification of highly complex SoCs as well as multi SoC systems
• Architect and develop functional verification environment, including reference models and bus-functional monitors and drivers
• Write a test plan using random techniques and coverage analysis, and work with designers to ensure it is complete
• Develop tests and tune the environment to achieve coverage goals
• Debug failures and work with designers to resolve issues
• Architecting, developing, and maintaining tools to streamline the verification of state-of-the-art multicore SoCs

Preferred Qualifications

No preferred qualifications provided.