DFT Engineer – ASICS Engineering
| Company | Qualcomm |
|---|---|
| Location | San Diego, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Senior |
Requirements
- Solid hands-on experience with industry standard DFT techniques such as scan and MBIST
- Strong fundamental knowledge of DFT
- Understanding of core-based test methodology and scan isolation
- Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware
- Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing
- Experience with industry EDA ATPG and insertion tools
- Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis
Responsibilities
- DFT pattern generation
- Coverage analysis and debug
- Running and debugging gate level simulations
Preferred Qualifications
- 5+ years industry experience in the implementation and verification of advanced DFT/DFD techniques for low power and multi voltage domain designs