DFT Engineer – Server – ASICS Engineering
| Company | Qualcomm |
|---|---|
| Location | San Diego, CA, USA |
| Salary | $164000 – $246000 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Senior, Expert or higher |
Requirements
- Bachelor’s degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- Master’s degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Solid hands-on experience with industry standard DFT techniques such as scan and MBIST.
Responsibilities
- Implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs.
- Deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies.
- DFT pattern generation, coverage analysis and debug.
- Running and debugging gate level simulations.
Preferred Qualifications
- Experience working on DFT for datacenter and/or 2.5D/3D chiplet products is strongly recommended.
- 8+ years industry experience in the implementation and verification of advanced DFT/DFD techniques for low power and multi voltage domain designs.
- Understanding of core-based test methodology and scan isolation.
- Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
- Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.
- Experience with industry EDA ATPG and insertion tools.
- Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis.