Dfx Engineer

10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
10+ years of DFx expertise encompassing multiple tapeouts for digital IP (CPU / GPU) and/or SOC projects
Demonstrated ability to architect DFT solutions from scratch on at least 1 project, and to create detailed specifications that can be used as a blueprint for implementation
Detailed understanding of test-coverage requirements across various scan modes especially as they pertain to bleeding-edge process nodes
Strong familiarity with RTL coding & STA with working knowledge of Physical Design
Strong post-silicon experience as it relates to debugging silicon behavior and test-escape issues
Crisp written and oral communication skills including working with global stakeholders
Thrives in fast-paced environment: i.e. yearly project tapeouts

Define the DFT architecture which optimally balances between coverage, test-time, and execution
Create a detailed implementation spec which documents details of the architecture including SOC-level interface, clock design, and support of various test/debug modes
Close on the spec with stakeholders including DFX / RTL / SOC / STA / PD teams
Implement DFT scan: RTL creation, LINT, timing-constraints, ATPG and simulation
Benchmark test-coverage and test-time to ensure that they meet expectations
Drive towards continuing DFX excellence: improving test-coverage, minimizing test-time, and exploring tools / methods that improve execution efficiency
Build strong collaboration with SOC and Product/Test Engineering teams to quickly resolve any silicon issues including test-escapes and yield loss

Familiarity with multi-voltage and multi-clocking domain implementation is a plus
Exposure to advanced approaches including hierarchical DFT and streaming fabric