Distinguish Engineer Design Verification

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 17+ years of related professional experience. OR Master’s degree in Computer Science, Electrical Engineering or related fields with 12+ years of experience. OR PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
Strong background in PCIe protocol and application with at least 10 years of experience in leading role of driving verification both at IP and SoC level in this area
Strong background in SoC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure)
Must have effective interpersonal and teamwork skills.
Participate in problem solving and quality improvement activities.
Demonstrate initiative and a bias for thoughtful action.
Grounded, detail-oriented, always backs up ideas with facts.

Lead a small team of engineers to define the verification methodologies for Marvell PCIe gen7 development that can enable robust product deployment and delivery across multiple products with PCIe I/F
Architect and implement simulation test bench in UVM
Develop and execute test-plans for verifying correctness and performance of the design.
Drive test logic with RTL designers to enable effective debugging both in pre-silicon validation and post silicon debug and bring up. Own and debug failures in both simulation and validation platforms to root-cause problems
Closely work with RTL designers of the block and SoC being verified for test plan development, execution, debug, coverage closure and gate level simulations
Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.

No preferred qualifications provided.