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DSP R&D Engineer
| Company | Broadcom Limited |
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| Location | Irvine, CA, USA |
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| Salary | $91000 – $146000 |
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| Type | Full-Time |
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| Degrees | Master’s, PhD |
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| Experience Level | Mid Level, Senior |
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Requirements
- Master’s and 3+ years of related experience; or PhD in Digital Signal Processing
- Knowledge in Communication Theory & Digital Signal Processing algorithms
- Experience in equalizers, Timing Recovery, Echo Cancellation and Gain Control algorithms
- Experience in C/C++, MATLAB/Simulink
- Good hands-on skills in the lab
- Good oral and written communication skills
- Experience in Wireline Algorithms
- Experience in Ethernet 802.3 PHY Transceivers
Responsibilities
- Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms
- Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation
- Develop and run system level simulation suites of the copper Ethernet PHY transceivers and perform vector matching verification with RTL simulations
- Define and document chip requirements, architecture, verification and lab test plan
- Lab testing and debug of ASICs
- Documentation/application note development and customer support
Preferred Qualifications
- Experience architecting communications systems for high performance ASIC based products is highly desirable
