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Formal Verification Engineer
| Company | Apple |
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| Location | Cupertino, CA, USA |
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| Salary | $111342 – $183600 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Entry Level/New Grad |
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Requirements
- Bachelor’s degree in electrical engineering, computer engineering, or related field with 0 years of experience.
- Detail oriented approach and desire to overcome challenges is required.
- Proficiency in any scripting language with excellent debugging skills.
Responsibilities
- Working with Apple Silicon’s world-class Security Enclave design engineers to develop a formal micro-architecture specification.
- Developing comprehensive formal verification test plan that includes unique security requirement verification.
- Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture.
- Crafting novel and creative solutions for modelling security attacks and proving robustness of complex design micro-architectures.
- Developing and implementing re-usable and optimized formal models and verification code base.
- Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.
Preferred Qualifications
- Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular design.
- Formal Method or Formal Verification technologies knowledge is a plus.
- Knowledge and experience in interpreting hardware specifications.
- Excellent interpersonal skills.
- Passionate about developing world-class/innovative formal verification solutions.
