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GNSS Design Verification Engineer
| Company | Apple |
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| Location | Sunnyvale, CA, USA |
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| Salary | $143100 – $264200 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Mid Level |
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Requirements
- BS with a minimum of 3 years of relevant experience.
- Experience with Wireless/DSP block/System-on-Chip verification.
- Advanced knowledge of SystemVerilog and in-depth understanding in UVM methodology.
- Solid verification skills in problem-solving, constrained random testing, and debugging.
Responsibilities
- Build block/subsystem/chip level testbench using outstanding DV methodologies.
- Build verification plan from specification and review with designers and systems engineers.
- Architect testbench with maximum reusability in mind and build UVM libraries.
- Generate directed and constrained random tests, debug failures, manage bug tracking, and close coverage.
- Create and analyze block/subsystem level coverage model and add test cases to increase coverage.
- Low power verification and formal verification.
- Improve DV flow and methodologies.
Preferred Qualifications
- MSEE or beyond is preferred.
- Knowledge of SOC subsystem and low power verification experience.
- Experience with SystemVerilog Assertion (SVA).
- Knowledge of scripting (like Shell, Python, and Perl).
- Experience in mixed-signal modeling and simulation.
