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Hardware Architect – Gpu – ML Ip

Hardware Architect – Gpu – ML Ip

CompanyGoogle
LocationMountain View, CA, USA, San Diego, CA, USA
Salary$156000 – $229000
TypeFull-Time
DegreesBachelor’s
Experience LevelSenior

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 5 years of work experience in ASIC hardware architecture and silicon design.

Responsibilities

  • Define and deliver the hardware Graphics/Machine Learning IP architecture that meet engaged power, performance, area and image quality targets, which will require owning the targets through to tape-out and product launch.
  • Collaborate with Graphics, Camera, Video, Display and Machine Learning software, system and algorithm engineers to co-develop and specify competitive hardware IP architectures for integration into SoCs.
  • Collaborate with GPU, TPU, camera ISP, video and display hardware IP design teams across global sites to drive the hardware IP architecture specifications into design implementation for SoCs.
  • Collaborate with SoC and System/Experience architects on meeting power, performance and area requirements at the SoC level for multimedia use cases and experiences.
  • Perform detailed data analysis and tradeoff evaluations to improve multimedia architecture solutions.

Preferred Qualifications

  • Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience architecting and designing low power multimedia hardware IP for SoCs in the following areas: Camera ISP, video codecs, display, graphics and machine learning networks.
  • Experience collaborating cross-functionally with product management, SoC architecture, IP design and verification, camera, video, machine learning algorithm and software development teams.
  • Experience in architecting ambient or always-on hardware and workflows for ultra low power SoC applications.
  • Experience in micro architecture, power and performance optimization.
  • Knowledge of interconnect/fabric, security, multi-level caching architectures.

Benefits

    No information provided on Benefits.