IC Design Engineer
Company | Broadcom Limited |
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Location | San Jose, CA, USA, Irvine, CA, USA |
Salary | $119000 – $190000 |
Type | Full-Time |
Degrees | Bachelor’s |
Experience Level | Expert or higher |
Requirements
- BS+12 Years of relevant industry experience. Advanced degree preferred
- Must have strong Logic Design, RTL coding (Verilog HDL) and debugging skills
- Must have an understanding of low power design and validation techniques including UPF/CPF
- Must be familiar with design constraint generation, logic synthesis, timing closure analysis and Clock/Reset domain crossing checks
- Must be able to assist in silicon and FPGA debug and bring-up
Responsibilities
- Participate in IP level architectural definition including micro-architecture definition
- Perform RTL design using Verilog HDL, with an emphasis on performance and area
- Implement multi-power and low-power designs
- Analyze and resolve Lint and Clock/Reset Domain crossing issues in the design
- Collaborate with verification team on test plan development, debugging, and coverage closure
- Collaborate with physical design team on constraint generation, timing closure analysis, formal verification, low power checks using UPF/CPF flows and ECO implementation.
- Support system level validation efforts on FPGA/emulation
- Support silicon bring-up and debug efforts
Preferred Qualifications
- Experience with the following are highly desired: ARM CPUs, Memory controllers, Peripherals such as I2C, SPI and UART, Peripherals and interconnect protocols such as APB, AHB and AXI
- Experience with the following are a definite advantage: Digital Signal Processing designs, usage of Matlab and Simulink, Scripting languages such as (Python perl/tcl), Mixed signal design