IP Enablement Engineer
| Company | Intel |
|---|---|
| Location | Santa Clara, CA, USA, Phoenix, AZ, USA |
| Salary | $186070 – $262680 |
| Type | Full-Time |
| Degrees | Master’s, PhD |
| Experience Level | Mid Level, Senior |
Requirements
- Master’s degree with 6+ years of Industry experience, or a PhD with 3+ years of Industry experience, in Electrical Engineering or in a STEM related field of study.
- Experience with IP standards i.e. (DDR/LPDDR/HBM, USB, MIPI, PCIe, USB, or HDMI).
- Experience in design and technology tradeoffs for IP i.e. (performance/power/area and cost).
- Experience in industry standard SOC design signoff methodology.
- Experience in SoC development life cycle including Silicon IP and SoC design, IP/EDA, design methodologies, and product lifecycle (PLC).
- Experience in technical program management of 3rd party IP vendors.
Responsibilities
- Driving closure of scope in the technical requirements in the RFQ stage, and in the Statement of Work (SoW). Verify IP release criteria defined in the SoW are met and IP is delivered with high quality and on time.
- Managing and driving to resolution technical and schedule dependencies with IP Ecosystem Partners throughout IP development and execution covering pre-silicon and post-silicon.
- Ensuring projects are well planned and executed on time with indicators and communication of project status.
- Identifying and managing risk.
- Work cross-functional dependencies and prioritizing support requests.
- Responsible for IP issue tracking and working with Foundry Design Technology Platform (DTP) team and Technology Development (DT) team to provide prompt feedback and solutions.
- Manage unified messaging between Partners and Intel stakeholders. Build and maintain solid relationships with senior leaders, strategic partners, and 3rd party EDA partners.
- Drive technical support for IFS Ecosystem IP development programs during IP lifecycle: High Speed Serdes IP – PCIe, Ethernet, D2D IP-UCIe, AIB Memory I/F – DDR, LPDDR, HBM- Mixed Signal IP’s – ADC, DAC, PLL- and Foundational IP – Embedded memories, Logic Libraries, GPIO.
- Partner with IFS teams as a subject matter expert to facilitate IP development through IP ecosystem partners.
- Influence and drive conflict resolution across stakeholders and vendors for win/win outcomes.
Preferred Qualifications
- IP standards and usage per market segment.
- Experience with Intel process technology or external foundries (TSMC).