Master Engineer

Master Engineer

Requirements

• Bachelors and 15+ years of related experience; at this level a post-graduate degree is typically expected or Masters degree and 13+ years of related experience or PhD and 10+ years of related experience
• Deep understanding of signal integrity and power integrity concepts such as characteristic impedance, s-parameters (RL, IL, FEXT/NEXT etc.), power plane impedance profile requirements and optimization etc.
• Strong authority on Cadence APD for custom substrate design
• Hands-on expertise of advanced and new assembly processes for flipchip, MCM packages, and 2.5D for advanced node silicon products (7nm, 5nm and beyond)
• Good understanding of materials as related to Chip Packaging Interaction (CPI)
• Familiarity with wafer BEOL as related to CPI (top metal, AP, passivation, UBM, bumping etc.)
• Knowledge of advanced substrate manufacturing/process is a must (e.g. SAP/mSAP, PSPI w/ Cu RDL etc.)
• In depth knowledge of failure analysis techniques on advanced node silicon (7nm, 5nm etc.) products with ELK and MiM structures
• Conceptual knowledge of package cost structure
• Strong project management, communication, and leadership skills
• Must have knowledge of GD&T and be able to read/comprehend mechanical drawings
• Good understanding of manufacturing and quality engineering fundamentals (DOE, process capability indices, etc.)
• Job requirements are broad; the candidate must be able to expand and grow in multiple disciplines (manufacturing/quality, materials, electrical, thermal, and mechanical)

Responsibilities

• Work with Business Units chip design team & Analog / Digital IP / Phy owners for new advanced node silicon chip floor plan & IP bump pattern design and optimization for package design requirements
• Work with business unit marketing and IC design teams to select the optimum package solution on cost, performance, manufacturability, and reliability for new advanced silicon node products
• Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages using Cadence APD
• Ensure designed packages meet CPI, SI/PI, and stringent thermal requirements (1000W+) of advanced node cutting edge silicon products
• Research, develop, and productize new materials such as TIM, build-up-film, underfill etc. in support advanced node silicon POR definition including bump cell definition
• Manage IC packaging activity from concept through development, qualification through high volume production
• Be a specialist and able to define assembly BOM, process, troubleshoot, support on packaging issues on new advanced technology
• Implement, fine-tune, and productize newly developed technologies into HVM
• Create package design documentation and assembly instructions
• Work close with QA and customers to resolve quality issues
• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification and production ramp
• Interface with other operations functional groups such as product engineering, foundry, test, and QA
• Participate in package technology development and/or other business productivity projects which have broad team impact
• Interface with tier #1 external customers for custom ASIC programs or as needed for development support, quality and/or other issue resolution
• Support NPI bring-up, pkg qual, and sustain support in production + multi-source activities for capacity, cost, & manufacturing flexibility needs

Preferred Qualifications

• Track record of innovation and subject matter expertise through journal publications and/or patent awards is desired
• Familiarity with advanced technologies such as 2.5D, 3D patterned structures such as inductors in package substrate, substrate technology is a plus