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Memory System Designer and Place and Route Engineer
| Company | Broadcom Limited |
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| Location | Mendota Heights, MN, USA |
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| Salary | $107000 – $171000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Senior, Expert or higher |
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Requirements
- Minimum of 8 years of relevant experience
- Bachelor in Electrical Engineering
- Strong design skills
- Ability to write and debug Verilog RTL code
- Place and route expertise
- Proficient in running STA, DRC, EM/IR tools, and attaining design closure
- Ability to code in Python
- Good understanding of synthesis tools and running synthesis
- Capable of running and debugging logical equivalency checkers
- Familiar with memory behavior
- Proficient in writing automation scripts
- Good communication, interpersonal, and leadership skills
- Motivated, self-driven, and good at multitasking
Responsibilities
- Architect and design memory subsystems
- Implement RTL of subsystem designs
- Place and route (physical design)
- Design closure: timing, DRC, LVS, EM/IR, etc.
- Gate netlist synthesis
Preferred Qualifications
No preferred qualifications provided.
