Mixed Signal Logic Design Engineer
| Company | Intel |
|---|---|
| Location | Santa Clara, CA, USA, Hillsboro, OR, USA, Folsom, CA, USA, Fort Collins, CO, USA |
| Salary | $139710 – $197230 |
| Type | Full-Time |
| Degrees | Bachelor’s, PharmD |
| Experience Level | Mid Level, Senior |
Requirements
- The candidate must have a bachelors or graduate degree in Electrical or Computer Engineering
- 3+ years’ of experience in RTL logic design and micro architecture experience
- 3+ years’ of experience in power management hardware and firmware design/support
- 2+ years’ experience with test-benches, simulation, validation and modeling theory is a plus
- 2+ years’ experience with C and perl programming skills are plus
Responsibilities
- Your duties will be applied within the entire scope of Front End and design development including micro architecture definition, writing system verilog RTL code per micro architecture spec, debugging failing tests, building simulation models, coding per power aware methodologies (UPF), and various FE tools and methodologies.
- Other responsibilities may include working with back-end designers in timing convergence and other silicon area optimization etc.
- Your work will directly contribute to the design and health of Intel architecture based next generation SOC products.
- Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
- Participates in the definition of architecture and microarchitecture features of the block being designed.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
- Supports SoC customers to ensure high quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.
- Strong written and verbal communication skills
Preferred Qualifications
- Knowledge and fundamentals in Logic design, computer architecture and VLSI design concepts
- Knowledge in system verilog language and other simulation tools like VCS