Multimedia/Graphics ASIC IP Hardware Architect
| Company | |
|---|---|
| Location | Mountain View, CA, USA, San Diego, CA, USA |
| Salary | $132000 – $189000 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Mid Level, Senior |
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience in ASIC Hardware architecture and silicon design.
Responsibilities
- Define and deliver the hardware Multimedia/Graphics ASIC IP integration architecture that meet competitive power, performance, area and image quality goals, which will require owning the goals through to tape-out and product launch.
- Collaborate with Graphics, Camera, Video, Display and Machine Learning software, system and algorithm engineers to co-develop and specify competitive hardware IP architectures for integration into SoCs.
- Collaborate with GPU, TPU, camera ISP, video and display hardware IP design teams across global sites to drive the hardware IP architecture specifications into design implementation for SoCs.
- Collaborate with SoC and System/Experience architects on meeting power, performance and area requirements at the SoC level for multimedia use cases and experiences.
- Perform detailed data analysis and tradeoff evaluations to improve multimedia architecture solutions.
Preferred Qualifications
- Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- Experience architecting and designing low power ASIC hardware IP for SoCs in the following areas, Camera ISP, video codecs, display, graphics and machine learning networks.
- Experience collaborating cross-functionally with Product Management, SoC architecture, IP design and verification, camera, video, ML algorithm and software development teams.
- Experience architecting ambient or always on hardware and workflows for ultra low power SoC applications.
- Experience in micro architecture, power and performance optimization.
- Familiarity with interconnect/fabric, security, multi-level caching architectures.