Physical Design – ASICS Engineering
| Company | Qualcomm |
|---|---|
| Location | Austin, TX, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Mid Level, Senior |
Requirements
- Good understanding of functional and test (DFT) mode constraints for place and route
- Floorplanning
- Power planning
- IR drop analysis
- Cell placement
- Multi-mode & multi-corner (MMMC) clock tree synthesis
- Routing
- Timing optimization and closure
- RC extraction
- Signal integrity
- Cross talk noise and delay analysis
- Debugging timing violations for MMMC designs
- Implementing timing fixes and functional ECOs
- Debugging and fixing physical violations
- Formal verification
- Deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C
Responsibilities
- Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies
- Be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs
- Develop and enable low power implementation methods
- Customize P&R to achieve area reduction, performance, and power goals
- Design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product
Preferred Qualifications
- 4+ years industry experience in Physical Design
- Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
- Timing closure experience in Synopsys PTSI
- Formal verification experience
- Power domain analysis experience
- Physical verification experience