Physical Design Engineer – Sr Engineer – ASICS Engineering
| Company | Qualcomm |
|---|---|
| Location | San Diego, CA, USA |
| Salary | $115600 – $173400 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Senior |
Requirements
- Bachelor’s degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field.
- Deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C.
Responsibilities
- Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
- Responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs.
- Development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals.
- Good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification.
Preferred Qualifications
- 3+ years industry experience in Physical Design.
- Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler.
- Timing closure experience in Synopsys PTSI.
- Formal verification experience.
- Power domain analysis experience.
- Physical verification experience.