Physical Design Engineer – Static Timing Analysis

Physical Design Engineer – Static Timing Analysis

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
• 5 years of experience in the domain of static timing analysis. (i.e., constraint authoring and verification, static timing analysis and timing ECO creation).
• Experience with EDA tools (i.e. Primetime or Tempus) and EDA Tcl commands (i.e., for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk).

Responsibilities

• Own timing constraint creation and validation, perform timing analysis and timing Engineering Change Order (ECO) creation, and oversee final timing sign-off for complex ASICs.
• Participate in both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
• Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
• Perform technical evaluations of EDA tools and provide recommendations, documentation and training.

Preferred Qualifications

• 8 years of experience in the domain of static timing analysis.
• Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
• Knowledge of semiconductor device physics, SPICE simulation and complex static timing topics, including complex clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification.

Benefits

No information provided on Benefits.