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Physical Design IP Integration Technologist
| Company | Google |
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| Location | Sunnyvale, CA, USA |
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| Salary | $132000 – $189000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Mid Level |
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Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience in analog design, integration, or validation.
- Experience designing or integrating analog physical interface (PHY) designs (e.g., PCIe, UCIe, or HBM PHYs).
- Experience with design integration flows and requirements.
Responsibilities
- Contribute to Physical Layer Device Design IP selection and procurement.
- Own Physical Design, IP planning, and roadmap definition.
- Drive pre-silicon integration of PHY Design IPs.
- Coordinate Physical Design IP requirements with cross-functional teams (e.g., Design, Verification, Physical Design, DFT, and Post-Silicon).
- Assist in post silicon bring-up and validation of Physical IP designs.
Preferred Qualifications
- Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
- Experience in writing design specifications.
- Experience in coordinating designs through the entire silicon product lifecycle.
- Ability to coordinate and execute across multiple cross-functional teams.
