Physical Design Low Power Verification – Lead – Vclp
| Company | Intel |
|---|---|
| Location | Marlborough, MA, USA, Austin, TX, USA, Santa Clara, CA, USA, Hillsboro, OR, USA, Fort Collins, CO, USA |
| Salary | $161230 – $227620 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Mid Level, Senior |
Requirements
- The candidate must have a Bachelor’s degree in Computer/Electrical Engineering or Computer Science and 4+ years of experience -OR- a Master’s Degree in Computer/Electrical Engineering or Computer Science and 3+ years of experience -OR- a PhD in Computer/Electrical Engineering or Computer Science
- Experience with owning the full chip level and taping out multiple complex SoCs.
- Leading the project from all the technical aspects right from RTL2GDS2.
- Experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc.
- Must have very good understanding of Full-Chip Level Partitioning, Floor planning, PnR, CTS, different clocking techniques for skew and delay balancing, multiple clock complexity, time budgeting, timing closure techniques, PnR congestion analysis, resolving floor planning issues, UPF (Low power design techniques), resolving formal verification, layout physical problems, understanding and hand-on experience of digital design sign-off tools like and not limited to noise analysis, layout closure, timing and functional eco closure, IR drop analysis etc.
- In-depth knowledge on RTL to GDS2 flow and understanding of basic device physics.
- Experience with internal flow development and understand nuances of Physical Design (Structural Design) flow.
- Minimum 2+ years’ experience with technically leading junior (fresh out of school) to senior/experienced individual contributors.
- Experience with handling developing PDKs (Process Design Kit)
- Working experience with cutting edge technology (5nm or below)
Responsibilities
- SD/Physical VCLP lead for Xeon projects to ensure multiple power domains are implemented correctly and correct by construction.
- Validation of insertion and connection of isolation cells, power switches, level shifters, retention registers and always-on cells throughout the implementation flow, from initial synthesis to place and route.
- Checks the correct functionality of isolation cells and power switches.
- Work with the Front End UPF, VCLP team to ensure correct by construction of the UPF, Low power Architecture.
- Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
- Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
- Supporting the team members in closing any design issues.
- Grooming the team members from the technical front.
- Knows how to handle Tape-out interaction with the foundry and worked on post-silicon activities.
Preferred Qualifications
- Scripting proficiency in PERL, TCL
- Should be able to own any technical task in SoC physical Design work
- Documented experience in technically leading past SoC full chip level physical design execution
- Exposure to various industry standard Physical Design and Sign-Off closure tools
- Knowledge of peer domains to Physical Design, viz., RTL, verification, DFx, post-Si etc.