Post Silicon Validation Engineer
| Company | PDDN |
|---|---|
| Location | San Jose, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Mid Level |
Requirements
- Strong background in SOC/VLSI/Mixed Signal IC bring-up
- Hardware debugging
- Proficiency in Verilog/VHDL
- Proficiency in C/C++
- Proficiency in Python
- Experience with silicon validation tools
Responsibilities
- Test plan development
- Hardware crafting
- Production test program release
- Collaborating with design teams on innovative IP solutions
Preferred Qualifications
-
No preferred qualifications provided.