Post Silicon Validation Engineer

7+ years of experience in bring up and debug of high speed and high power SoCs
7+ years of experience in silicon validation planning and leading a project from pre silicon planning, bring up, full SoC validation, and characterization to providing validation signoff before HVM
Comprehensive knowledge of Embedded software programming
Proficient in programming languages such as C, C++, Python, TCL and Shell scripts
Strong protocol knowledge in I2/I3C, SPI, UART, JTAG, and PCIe
Strong understanding of FPGA programming
Proficient in High Speed SerDes testing
Proficient in TCP IP, UDP, IPv4, IPv6 addressing, Ethernet, DHCP, and DNS
Hands on experience with high speed oscilloscopes and debugging embedded systems using logical analyzers
Basic understanding of how LLMs work
Some experience with DFT (Design For Test)
Experience in automation framework development using Python or any other language
Good knowledge of ASIC design flow and silicon FW development process
Flexible to adapt to a very dynamic environment and always carrying forward key improvements

Responsible for developing an E2E system validation test plan for the SoC including characterization
Collaborate with the SW teams to develop a complete suite of tests that enable maximum system level coverage for validation and characterization
Collaborate with the HW teams to develop the optimum solution for test validation and characterization
Responsible for understanding the SoC design to collaboratively work with cross functional teams to create, modify, edit tests and suggest coverage improvements
Responsible for supporting correlation between system and other key platforms to enable a robust production plan

Basic understanding of how LLMs work
Flexible to adapt to a very dynamic environment and always carrying forward key improvements