Principal Design Verification Engineer

Principal Design Verification Engineer

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
• Strong background in PCIe protocols and applications with at least 3 years of experience
• Strong background in SOC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
• Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure).

Responsibilities

• Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.
• Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
• Developing tests and tuning the environment to achieve coverage goals.
• Debugging failures and working with designers to resolve issues.
• Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.
• Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
• Unit and regression testing of software tools.

Preferred Qualifications

• Effective interpersonal and teamwork skills.
• Participate in problem solving and quality improvement activities.
• Demonstrate initiative and a bias for thoughtful action.
• Grounded, detail-oriented, always backs up ideas with facts.
• Ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.