Principal Design Verification Engineer - Coherent Interconnect

Principal Design Verification Engineer – Coherent Interconnect

20+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 18+ years of experience with a Master’s degree, or 16+ years of experience with a PhD
15+ years of professional experience in a design verification role
Must have experience with Coherent Interconnect; Combined experience with LPDDR memory controllers is a plus
Proficient with ARM protocols – CHI, AXI, ACElite, APB
Expert hands-on coding skills in System Verilog, UVM
Experience with Git version control, Unix/Perl scripting
Good written and verbal communication skills
Formal verification skills will be a plus

Contribute to the functional verification of System IP including coherent interconnect, caches, and dynamic memory controllers
Act as the go-to person for technical know-how and micro architecture
Architect and build re-usable testbenches right from scratch
Identify shortcomings of existing verification flows and propose new solutions
Propose and drive best practices and methodologies that can improve productivity
Own key features and timely execution of tasks as per milestones
Create test plans as per spec, challenge spec and testplan/code reviews
Work with designers to resolve any spec issues
Create verification environments, stimulus, and tests
Collaborate with designers to verify the correctness of a design feature and resolve fails
Develop assertions, checkers, covergroups, and Systemverilog constraints
Debug and root cause functional fails from regressions
Analyze code and functional coverage results and perform gap analysis
Identify coverage exclusions and improve stimulus
Work with SoC team to debug functional fails during IP bringup and feature execution
Collaborate with Physical design teams, running and debugging gate-level simulations
Work with Performance verification teams to help with co-sim TB bringup
Bringup power-aware verification with UPF
Help with Silicon bringup and root causing fails
Mentor junior team members