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Principal Engineer – Analog IC Design
| Company | Marvell |
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| Location | Santa Clara, CA, USA |
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| Salary | $180000 – $210000 |
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| Type | Full-Time |
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| Degrees | Master’s |
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| Experience Level | Mid Level, Senior |
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Requirements
- Master’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field
- Three (3) years of experience in the job offered or related occupation
- Experience with Cadence ADE tool
- Experience with XSR RX CLKTOP sub-block design
- Experience with XSR_PHY Top layout review
- Experience with DDR45 RX AFE sub-block design
- Experience with D2D RX TOP design
- Experience with SSPLL_5P0G_LP design and SoC supporting
- Experience with LVD_ADC design and SoC supporting
- Experience with multiple miscellaneous IPs (opamp, bandgap, regulator) design and SoC supporting
Responsibilities
- Perform circuit design and layout design in high speed Serdes
- Optimize circuit to achieve high performance and meet customer requirements
- Own and maintain TSMC 3nm Receiver Clock Top
- Use designing DLL, Phase Interpolators, High Speed Clock Drivers related to SerDes Application for 112G and above for ethernet applications
- Own and maintain TSMC 3nm Receiver Top Design for D2D PHY
- Work extensively on Marvell’s Central Analog Library for 7nm, 5nm and 3nm
- Responsible for a variety of fundamental building block designs used in high-speed integrated circuit design
Preferred Qualifications
No preferred qualifications provided.
