Principal Engineer – High-Speed DDRPHY Architect
| Company | Intel |
|---|---|
| Location | Santa Clara, CA, USA, Hillsboro, OR, USA, Folsom, CA, USA, Worcester, MA, USA, Phoenix, AZ, USA |
| Salary | $214730 – $303140 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s |
| Experience Level | Senior, Expert or higher |
Requirements
- Master’s with 8+ years of experience in Electrical/Computer Engineering or related field or BS with 12+ years of experience in Electrical/Computer Engineering or related field
- 12+ years of DDR I/O and other High Speed IO interface development experience
- Prior hands-on experience in DDR IO PHY Architecture and Design
- Strong knowledge of DDR5 Protocol
Responsibilities
- Lead the architectural definition and integration of high-speed DDR PHYs for Server SoCs, including DDR6, DDR5, MRDIMM, RDIMM, LPDDR etc.
- Collaborate with platform and product architects to analyze requirements and define critical performance, power, and area specifications to ensure the success of our products.
- Conduct technical evaluations of both internal and external PHY IPs, analyzing their performance characteristics against product requirements, and ensuring strategic alignment with overall product goals.
- Define detailed IP requirements, lead vendor engagement, and make strategic IP selection recommendations based on technical feasibility, cost-effectiveness, and long-term roadmap alignment.
- Proactively research and evaluate emerging DDR I/O technologies, industry trends, and evolving standards.
- Identify and champion opportunities to incorporate these advancements into our product roadmap, enhancing performance, power efficiency, and feature sets, and positioning our products for competitive advantage.
- Create clear and comprehensive architecture specifications and rigorous integration guidelines.
- Provide review and constructive feedback on related architectural specifications to ensure alignment with overall SoC goals.
- Provide technical guidance and mentoring to junior engineers, fostering their growth and contributing to the overall team expertise.
- Champion a collaborative environment across multiple teams.
- Serve as a technical lead in the post-silicon debug and validation of high-speed I/O interfaces, leading taskforces and driving the resolution of complex issues.
- Oversee the validation process to ensure seamless and high-quality implementations.
Preferred Qualifications
- High familiarity with Industry trends within the DDRIO domain and ability to map them to Intel roadmap/products and segment strategies