Principal Memory Controller Micro-Architect/Logic Designer

20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
Experience working with memory controller u-architecture
Must have an in-depth understanding and experience with different memory technologies like LPDDR4/5/6, PIM, DDR, GDDR, HBM
Knowledge of JEDEC memory standards required
Working knowledge of DDR PHY
Strong background owning and driving the RTL design of all sub-blocks of custom memory controller designs
Demonstrated experience of successful Architectural through RTL design on high performance digital designs
Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis & ECO
Strong communication and interpersonal skills are required, along with the ability to work in a dynamic, global team
Experience with a scripting language like Perl or Python

You drive the timely development and debug of new features on timely development of custom memory controller
You are familiar with JEDEC standards and timing parameters
You have working knowledge of DDR PHY
You work on SOC IP delivery with all sanity checks
You work on timing debug and closure
You work on LINT, CDC flows and analysis
You work on power artist flow and power analysis
You have experience working on ECO flows
You collaborate with the verification team to verify the functionality and correctness of the design
You communicate with implementation to achieve your timing and area
You produce high quality RTL on schedule meeting PPA goals
You engage with performance and power team on achieving performance and power goals
You partner with the physical design and CAD team to resolve implementation level details