Principal/Sr. Principal IC Design Engineer
| Company | Northrop Grumman |
|---|---|
| Location | Halethorpe, MD, USA, Rancho Cordova, CA, USA |
| Salary | $105400 – $206000 |
| Type | Full-Time |
| Degrees | Bachelor’s |
| Experience Level | Senior, Expert or higher |
Requirements
- Bachelor of Science STEM (Science, Technology, Engineering, Mathematics) degree with 5 years of experience in Analog, Digital or Mixed Signal Circuit design (3 years with technical MS or 0 years with a PhD) for Principal IC Design Engineer
- Bachelor of Science STEM (Science, Technology, Engineering, Mathematics) degree with 9 years of experience in Analog, Digital or Mixed Signal Circuit design (7 years with technical MS or 4 years with a PhD) for Sr. Principal IC Design Engineer
- Demonstrated experience with hands-on custom circuit design
- Experience with IC custom design tools (Cadence Virtuoso) for schematic capture, circuit simulation, and custom layout; physical verification using Assura or Calibre
- Demonstrated experience in problem solving and analytical skills
- Demonstrated experience in meeting tight deadlines and milestones according to program schedule
- Excellent communication skills, able to efficiently disseminate information to leadership and respective working group
- Able to obtain and maintain a TS/SCI with polygraph security clearance per business requirements
- US Citizenship required
Responsibilities
- Tasks will include schematic capture, circuit simulation, circuit layout, physical verification (LVS, DRC), and parasitic extraction for a variety of analog and mixed signal circuits
- The right candidate will have experience in custom circuit design with Cadence Virtuoso and modeling circuit performance using ADE/Spectre
- The candidate must be able to take a design from concept through modeling, layout and verification and create a test plan based on circuit requirements
Preferred Qualifications
- Experience architecting, designing, and simulating low power analog integrated circuits with multiple successful tapeouts in planar and/or advanced CMOS nodes
- Experience with hierarchical design, top-level floor-planning, and chip-level integration
- Experience in low power analog and mixed signal design work including voltage references, LDO regulators, data converters, power on reset, brown-out detection, and temperature sensors
- Experience using Verilog, Innovus and Verilog-A/AMS
- Experience in scripting languages SKILL or Python
- Experience with product validation and testing
- Basic understanding of IC manufacturing and testing processes
- Active TS/SCI Security Clearance