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RTL Design Engineer
| Company | Apple |
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| Location | San Diego, CA, USA |
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| Salary | $135400 – $250600 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Mid Level |
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Requirements
- BS degree in technical discipline with minimum 3 years of proven experience.
Responsibilities
- Gain knowledge in designing micro-architecting digital blocks within sophisticated mixed-signal circuits.
- RTL coding of blocks specified by you or others.
- Participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and interacting with the design verification team.
- Participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Preferred Qualifications
- Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog
- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
- Validated knowledge of synthesis, static timing, DFT, is a plus
- Validated knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus
- Knowledge of scripting languages. Perl and Python are plusses
- Strong communication and presentation skills
