RTL Design Engineer – Coherent Interconnect
| Company | Samsung |
|---|---|
| Location | Austin, TX, USA |
| Salary | $122220 – $189442 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Mid Level, Senior |
Requirements
- 3+ years of experience with a Bachelor’s degree in Computer Science/Engineering/related field, or 1+ years of experience with a Master’s degree, or a PhD.
- Strong foundation in digital design principles and RTL design experience.
- Verilog expertise is required; Experience with scripting languages such as Perl or Python.
- Proven track record of delivering high-quality designs with excellent performance, power, and area characteristics.
- Excellent communication and collaboration skills, with ability to work effectively in a team environment.
- Strong problem-solving skills, with ability to debug complex design issues and optimize design performance.
Responsibilities
- You design and develop RTL code for System IP components, including coherent interconnect, last level cache (LLC), and memory controllers.
- You optimize design performance and power consumption to meet project requirements.
- You perform logic debug and timing closure to ensure design functionality and meet timing specifications.
- You work closely with system architects to ensure design meets system-level requirements and performance goals.
- You collaborate with verification teams to develop and implement comprehensive verification plans.
- You partner with design implementation teams to ensure seamless integration of System IP into larger SoC designs and resolve implementation level details.
Preferred Qualifications
- Knowledge of Memory subsystem, memory controller, coherency, fabric and system caches is highly preferred.