RTL Design Engineer – University Graduate – PhD – Machine Learning
| Company | |
|---|---|
| Location | Madison, WI, USA, Sunnyvale, CA, USA |
| Salary | $132000 – $189000 |
| Type | Full-Time |
| Degrees | PhD |
| Experience Level | Entry Level/New Grad, Junior |
Requirements
- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog.
Responsibilities
- Work mostly independently to create and review clock control subsystem’s design microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with architecture and power teams to evaluate features and their impact.
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
Preferred Qualifications
- Experience with digital clock control circuits.
- Experience interacting with software, architecture, and other cross-functional teams.
- Experience with a scripting language (e.g., Python or Perl)
- Knowledge of processor design or accelerators.
- Knowledge of high-performance and low power design techniques.