Senior ASIC Design Verification Engineer

BSEE (or equivalent experience) with 5+ years’ experience in unit level or sub-system level verification or MS preferred in Electrical, Computer Engineering with 3+ years’ experience in unit level or sub-system level verification
Proficiency with Object Oriented Programming, System Verilog, Verilog, UVM, SVA and Functional Coverage
Strong skills with VCS or equivalent simulation tools like Questa is required
Strong debugging and analytical skills are required
Have a continuous improvement mentality and passionate about delivering bug-free first silicon
Strong interpersonal skills and ability to work with on-site and remote teams is a plus

Work as part of Global Circuits Team to develop various innovative IPs for hardware security, clocking, voltage regulation and silicon correlation
Own the unit and sub-system level verification of various IPs, create functional test plans, and verify using advanced verification tools, flows and methodologies
Build and reform world class verification infrastructure and methodologies to meet the unique demands of custom designed IPs
Engage in design specification development by participating in discussions on architecture, intent, and implementation of the various IPs
Enable system level integration by working with partner teams for test development & debug and delivering Verification IPs

Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies is a huge plus
Strong knowledge or work experience in Mixed signal and custom designed IPs solutions
Good understanding of behavioral real number modeling and low level digital or mixed signal design concepts
Strong knowledge or work experience in co-simulation environments such as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains
Proficiency in scripting language, such as, Perl, Tcl, Make files and automation methods/algorithms a certain plus