Senior ASIC Design Verification Engineer

BS degree in electrical engineering, or related fields, or equivalent practical experience; advance degrees (MS or PhD) is a plus
10+ years design verification experience of building testbenches environments and design verification processes

Verify hardware features of Language Process Unit (LPU).
Collaborate within the Hardware Team to design and verify features on LPU chips in simulation, emulation and silicon.
Develop and implement advanced verification environments and methodologies for complex ASIC designs.
Implement and optimize automated verification flows to improve productivity and efficiency.
Utilize formal verification techniques to rigorously verify critical design properties and ensure compliance with specifications.
Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process.
Support silicon bring-up and debug.
Be a productivity multiplier. Contribute to identifying and adopting engineering best practices within the verification team and interactions with cross-functional teams at Groq.
Innovate. Contribute to developing future verification strategies for validating future accelerator chips and hardware architectures for ML workloads.

Excellent verbal and written communication skills to clearly communicate concepts in written and verbal form to stakeholders.
Experience with building block and SOC testbench development
Good familiarity with SystemVerilog and UVM
Good familiarity with randomly constrained testing methodologies.
Good familiarity with power verification strategies and UPF
Good familiarity with netlist simulation
Good familiarity with formal verification flow and tools
Experience in Python and/or Perl scripting
Knowledge of ASIC design flow
Knowledge of applying machine learning to ASIC verification flow
Knowledge of silicon bring-up, debug, and manufacturing ATE support
Proven track record of delivering bug-free silicon