Senior ASIC Design Verification Engineer – ASICS Engineering

Senior ASIC Design Verification Engineer – ASICS Engineering

Requirements

• Strong SystemVerilog / UVM based verification skills, experience with assertions, and coverage-based verification methodology
• Strong debugging, Analytical and problem-solving skills
• Experience in formal / static verification methodologies will be a plus
• Good understanding of WiFi or other wireless communications standards is a plus
• Experience with GLS, and scripting languages such as Perl, Python is a plus
• Bachelor’s degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience OR Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience OR PhD in Science, Engineering, or related field.

Responsibilities

• Understanding of WLAN PHY TX and RX design paths
• Verifying algorithms that control the various aspects of wireless systems
• Develop test plans to verify WiFi Standards, creating test sequences, and validating design components
• Own end-to-end DV tasks from coding Test benches, test cases creation, crafting assertions, running simulations, and achieving all coverage goals
• Explore innovative DV methodologies (formal, simulation, and emulation strategies) to continuously push the quality and efficiency of test benches
• Successful candidate will be required to collaborate with worldwide design, silicon, and architecture teams to achieve all project goals.

Preferred Qualifications

• Master’s degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 3+ years of ASIC design, verification, validation, integration, or related work experience.
• 2+ years of experience with architecture and design tools.
• 2+ years of experience with scripting tools and programming languages.
• 2+ years of experience with design verification methods.